A static synchronous compensator based on the hybrid cascaded multilevel converter (HCMC-STATCOM) is studied. The DC voltage of a two-level converter and the number of H-bridge sub-modules in wave-shaping circuit (WSC) are optimized. The DC capacitor ripple voltage of the two-level converter and WSC has been mathematically modeled to provide a theoretical basis for the parameter design of the DC capacitor. Comparison of the HCMC-STATCOM with the cascaded STATCOM shows that: the HCMC-STATCOM has less modules of cascaded H-bridge while appreciably reducing the DC capacitor capacity

which means the cost and size of the device will be reduced. A simulation platform of 35 kV/±100 Mvar HCMC-STATCOM has been built on PSCAD/EMTDC. The results of the simulation have verified the feasibility of the topology and the correctness of the theoretical analysis.