This paper proposes a new three-phase phase-locked loop（PLL）consisting of a frequency-locked loop（FLL）and an initial phase angle PLL.The FLL employs a new differential algorithm to detect frequency error.The algorithm is able to bypass frequency detection error caused by phase jumps and voltage abrupt changes.The proposed PLL employs a frequency adaptive digital filter（FADF）to filter harmonics and noises in the input voltage.The FADF employs multistage delayed signal cancellation（DSC）to eliminate low-frequency harmonics.Then higher frequency harmonics and noises are removed by the Butterworth low-pass filter.The FADF can quickly and accurately extract the fundamental frequency positive sequence in the dq domain.Meanwhile，the initial phase angle PLL has a high natural frequency which makes it possible for the proposed PLL to rapidly realize synchronization after phase angle jumps.Simulations and experiments have proved the effectiveness of the proposed PLL.For its application in low cost controllers，a simplified algorithm of the PLL is presented.