High stability and accuracy synchronous sampling clocks are required in the realization of digital substations. The key to meeting this requirement is to find a way to eliminate the errors of the synchronous sampling clock by effective compensation. By analyzing the causes of generation of the GPS clock errors and using the GPS clock error distribution characteristics， the relative stability of the frequency of the crystal oscillator within a short time， and the characteristics of the high speed digital signal processing by FPGA， and aided by the corresponding measures， it has been possible to eliminate the influence of the frequency deviation of the crystal oscillator on the sampling clock error and realize man-made incorporation of one or more clocks should rather apparent deviation or perturbation occur within a short time， thereby guaranteeing accurate synchronization of the sampling clocks and providing the design and application of the prevailing digital substations with a highly stable and accurate design method for synchronous sampling clocks.