In view of the rather high requirement of time performance for the merging unit in the smart substation，through the concrete analysis on the implementation principle of the merging unit using the interpolation algorithm，and by fully utilizing the computing performance of PowerPC together with the parallel processing capabilities of FPGA，the whole system is divided into several cooperated models and a design solution of key links for merging unit is presented.In this solution，a high precision time-keeping model is realized by the statistics and records for the continuous and effective pulse per second（PPS）interval.To realize synchronization with the external time signal，a dynamic adjustment method for time resampling is presented through the flexible setting for interrupted cycle of timer.At the same time，an equal interval output of SV9-2datagram is accurately realized through the division of output delay and caching feature of FPGA.