An entire digital synchronous sampling algorithm for high accuracy harmonic measurements is proposed. The basic idea of this algorithm is to dynamically adjust the decimation ratio of the decimation filter of a sampling analog-to-digital converter（ADC） in accordance with the fundamental frequency of the electric power systems. By doing so， the average sampling frequency of the decimated output can change with the input signal frequency. Compared to the traditional analog phase locked loop（PLL） and software synchronous sampling methods， the features of the proposed algorithm is of hardware simplicity and compact in space， thus make it suitable for mixed-signal realization. A Simulink simulation model including a delta-sigma ADC， a frequency estimation module， a decimation ratio adjusting control unit and a 64-point fast Fourier transform（FFT） calculation engine is built for the application of an actual mixed signal system chip design. When the sampling frequency of the delta-sigma ADC is 1.638 4 MHz， and the bandwidth（can measure harmonics up to 31st） of the input signals is 1.6 kHz， the simulated fundamental and harmonic root mean square（RMS） errors are respectively lower than 0.001% and 0.02% after synchronous sampling with fundamental frequency variation of±5%.