The enhanced PLL（EPLL） has more advantages in speed and stability than the general phase-locked loop. The synchronous signals of multiple frequencies generated by the EPLL can synchronize the asynchronous data. After the quasi-synchronous data is processed in the FFT module， the accurate results of the harmonic analysis can be rapidly obtained. A logic circuit using the EPLL is proposed for the whole process of harmonic analysis. The circuit has been implemented in FPGA. Influences of three main error sources in harmonic analysis accuracy， including the sampling in different spaces， the transformation from asynchronous data to synchronous data and the truncation errors in fixed-point arithmetic， are investigated. The logic circuit has been utilized in a power measuring chip with harmonic analysis.