A digital hardware control scheme of shunt active power filter（SAPF） based on field programmable gate arrays（FPGA） is introduced. Several strategies， such as algorithmic strength reduction， folded architecture and pipline method， are addressed to optimize hardware architecture and system operating frequency. An efficient controller including synchronous reference frame theory based distortion detection， infinite impulse response（IIR） low-pass filter， three-phase phase-locked loop（PLL）， and hysteresis current controller is designed. The entire control scheme of SAPF is developed on a single FPGA using VerilogHDL. Experimental results achieved from a prototype show the steady state and dynamic performance of the SAPF system with real-time and accurate control.